Website : www.lsi.com
Job Position : Physical Design Engineer
Eligibility : B.Tech/BE/MTech/PhD
Experience : 0 - 1 Year
Location : Bangalore
Job Description :
A Bachelors/Masters/Phd Degree in engineering from Teir I (IIT/NIT/IISC only), with exceptional academic credentials. Good oral and written communication skills are needed.
Job responsibilities will covers all aspects of the ASIC and ASSP design implementation process starting from the release of RTL through design tapeout. Candidates must be keen to able to take up projects that span ASIC diesizing and package evaluation, RTL analysis, synthesis, STA constraint development and use, design for test, timing closure, layout and ECOs, power analysis, signal integrity checks, DRC/LVS, final design signoff, and GDS2 tapeout.
As an integral member of the customer design engineering team, the ASIC Customer Engineer has responsibility for a wide range of tasks, including chip floor planning, place and route, timing analysis, signal integrity, test, and design verification. Responsible for support and completion of designs from customer provided RTL or Gate level netlist using the latest LSI technologies.
Desired Profile :
A Bachelors/Masters/Phd Degree in engineering from Teir I (IIT/NIT/IISC only), with exceptional academic credentials. Good oral and written communication skills are needed.
Job responsibilities will covers all aspects of the ASIC and ASSP design implementation process starting from the release of RTL through design tapeout. Candidates must be keen to able to take up projects that span ASIC diesizing and package evaluation, RTL analysis, synthesis, STA constraint development and use, design for test, timing closure, layout and ECOs, power analysis, signal integrity checks, DRC/LVS, final design signoff, and GDS2 tapeout.
As an integral member of the customer design engineering team, the ASIC Customer Engineer has responsibility for a wide range of tasks, including chip floor planning, place and route, timing analysis, signal integrity, test, and design verification. Responsible for support and completion of designs from customer provided RTL or Gate level netlist using the latest LSI technologies.
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